Electronics designers continually adapt their designs to account for changes in design approaches and electronics technology. One such design issue encountered is the increase of the relative process variability between nodes, such as when transitioning from 45 nm to 28 nm. This variability generally results in circuit designers adding additional margins to their designs to account for uncertainty in operational circumstances, such as spatial transistor variations, local transistor mismatch, VT skew, and interlayer interconnect variation. Designs of ICs such as digital logic circuits formed from electronically connected digital logic cells, therefore, are increasingly being affected by inherent variations in the digital logic cells, which result from IC performance affecting parameters, such as resulting from variation in manufacturing processes. 
Current design approaches require designers to be aware of and account for process variations for each digital logic cell, such as the most basic standard two transistor CMOS inverter cell. Variations in the supply voltage and/or ground reference voltage result in changes in the time required for the cell to process the input signal to produce the output signal, such as indicated in its delay time (also referred to as the cell delay), rise time and fall time parameters.
Increased variations in cell delays produce a significant increase in the worst-case cell delays over the nominal delays. In some cases, the worst-case delays may be so significant that traditional logic design methods are rendered ineffective.
Further, standard logic cells are generally produced having standard drive strengths. Thus, designers generally limit and/or adjust their designs to utilize the available standard drive strengths. As used herein, the rise or fall time of a cell resulting from fabrication with a strong process is defined to be less than the rise or fall time of a cell resulting from a weak process. Changing a cell to utilize a different drive strength may result in the need for the entire cell to be redesigned and the IC refabricated with the new element, which further increases development time and resources.
Attempts to overcome this performance variation problem have generally focused on utilizing mathematical model and specially-developed algorithms to model the cell delay or other timing parameter. In the case of cell delays, for handling large worst-case delays, a statistical timing analysis methodology can be used to model the rise and fall times as random variables. The statistical models are then used by the designer to check for critical paths and close timing, rather than designing the logic to meet the worst-case rise time. Specially-developed  algorithms add complexity to the solution, and, therefore, increase the time required to analyze the solution and develop the IC product.